Wave digital filters (WDFs) are a sub-class of digital filters which are considered to have a good dynamic range, low round-off noise, and inherent stability. WDFs are especially useful in digital processing when it is desired to minimize the number of bits used in the filter's coefficients. A general description of WDFs may be found in Alfred Fettweis, “Wave Digital Filters: Theory and Practice”, proceedings of the IEEE, Vol. 74, No. 2, February 1986, the disclosure of which is incorporated herein by reference.
WDFs generally comprise a plurality of cascaded adapters, memory elements and inverters, which are organized to form digital equivalents of known analog filters. The memory elements and inverters are used to construct digital equivalents of basic analog elements, such as capacitors and inductors, and the adapters are used to interconnect the memory elements and inverters which represent the different basic analog elements of the known analog filters.
The adapters are combinatorial (memoryless) elements which include multipliers and adders. Generally, the adapters have a plurality of ports, usually either two or three ports, each port including an input and an output.
FIGS. 1A and 1B are a schematic block diagram of a seventh order WDF 20 known in the art. WDF 20 comprises seven cascaded three port adapters 22. Each adapter comprises three input lines (In1, In2, In3) and three output lines (Out1, Out2, Out3). One of the ports, of each adapter 22, is preferably connected to a respective register 24 which stores an internal state value of WDF 20. The other two ports of each adapter 22 (except the extreme adapters 22A and 22G) are connected to respective ports of neighboring adapters 22. Adapter 22A preferably receives an input value of filter 20 through its input line In1 26, and adapter 22G provides an output of the filter on its Out1 output line 28. Typically, a constant zero value is provided to the In1 input line of adapter 22G. It is noted that the orientations of adapters 22, i.e., their port connections, vary.
The seven adapters 22 comprise four constrained serial adapters 22A, 22C, 22E and 22G, two constrained parallel adapters 22B and 22F, and a single unconstrained parallel adapter 22D. Constrained serial adapters 22A, 22C, 22E and 22G are governed by the following equations:Out1=In1−α(In1+In2+In3)Out2=In3−Out1 Out3=−In1−In2  (1)
Constrained parallel adapters 22B and 22F follow the following equations:Out1=In3+(1−α) (In2−In1)Out2=In3−α(In2−In1)Out3=In2−α(In2−In1)  (2)
Unconstrained parallel adapter 22D follows the following equations:Out1=In3+(1−α1)(In3−In1)−α2(In3−In2)Out2=In3−α1(In3−In1)+(1−α2)(In3−In2)Out3=In3−α1(In3−In1)−α2(In3−In2)  (3)
In these equations α, α1, and α2 are coefficients of the respective adapters 22, and have values determined separately for each adapter. It is noted that different types of adapters have different numbers of coefficients. The coefficients determine the frequency response (i.e., the transfer function) of the WDF. Methods for selecting appropriate values for the coefficients are described, for example, in the above mentioned reference of Alfred Fettweis.
As with other filters it is desired to minimize their power consumption.
For compactness of the adapters, in order to save, time, space and power consumption, the different outputs of the adapters are calculated using common hardware. For example, in the constrained serial adapters, the result of calculating Out1 is used in calculating Out2. FIGS. 2A, 2B and 2C are schematic illustrations of the structures of a constrained serial adapter 30, a constrained parallel adapter 32 and an unconstrained parallel adapter 34, known in the art. Adapters 30, 32 and 34 are specific implementations of adapters which may be used as the adapters 22 of filter 20. Adapters 30, 32 and 34 comprise adders 52, inverters 54, and multipliers 56, organized in a manner which carries out, respectively, equations (1) (2) and (3).
A paper titled “Design of Wave Digital Filters with Minimal Coefficientlength” by Manshanden and Nouta, Delft University of Technology, The Netherlands, Sep. 11, 1997, the disclosure of which is incorporated herein by reference, suggests reducing the length of the coefficients multiplied by the adapters of a WDF, in order to reduce the chip die size of the WDF. In addition, the paper suggests reducing the chip die size and the power consumption of a WDF by limiting the number of ‘1’ bits in the coefficients. Still, additional reduction in power consumption is desired.